Chip oriented technologies are playing an ever increasing role in product innovation and improvement. While chip complexity is approaching the 1 megabit milestone, products often require more capabilities than can be adequately incorporated in a single chip. Moreover, it is often preferred, particularly in the case of extensive large scale systems such as super computers, that the system not be over-integrated to avoid the possibility that an entire expensive assembly may have to be scrapped because of the failure of a relatively minor part. Accordingly, it is becoming increasingly common for chip oriented technologies to be implemented as chip sets comprising a plurality of individual chips designed to be interconnected and to interact in a pre-specified manner. A typical chip set might, for example, include chips which provide a microprocessor, one or more interface chips, a permanent memory such as a read only memory (ROM), and a volatile storage such as a random access memory (RAM). While chip sets can contain as few as two or three chips, chip sets for computers typically contain several hundred or even thousands of chips. VLSI chips in a set may typically include up to 64 or more external connections and the majority of these connections are directed to interfacing with other chips.
One of the difficulties in using a large set of chips, however, is the fact that the various chips must communicate with one another. Each chip in the set must have sources of power and ground potentials, and the conductive elements which provide the power and ground connections sized appropriately to handle the required current for the package and must be well insulated from each other, especially where chip voltages are relatively high. In addition, the chips in the set must communicate with each other which usually entails a rather complex interconnection scheme.
Information processing equipment such as computers or other signal processors employ chip sets containing hundreds or thousands of chips. The cost of these systems directly relate to the cost of packaging and interconnecting the chips in a set in a desired functional relationship. Further, the operating speed of a system and the chips comprising the system play an important role in the successful implementation of new technologies. Interconnections between chips contribute to signal propagation delay and signal distortion. In addition, the packaging system must be capable of dissipating as much heat as it generates in order to maintain thermal equilibrium. Conventional packaging systems employing printed circuit boards are unable to handle the required number of chips within a volume and at a density which is readily compatible with the requirements of more advanced circuit applications. Moreover, chips disposed on an exposed substrate are susceptible to contamination.
This invention is directed to a package for holding and interconnecting a plurality of chips into an operational unit. The package is intended to provide a contamination free environment, connection runs of minimum length, and a thermally stable containment for the chips.
A silicon circuit board which incorporates multiple levels of patterned conductors similar to that employed in the disclosed invention is described in U.S. Pat. No. 4,541,035 issued to R. O. Carlson, H. H. Glascock, J. A. Loughran, and H. F. Webster, for a Low Loss Multilevel Silicon Circuit Board. The substrate interconnection arrangement of this invention bears some resemblance to the interconnecting board described in the above referenced patent.
U.S. patent application Ser. number 912,456, filed Sept. 26, 1986 now U.S. Pat. No. 4,783,695, issued Nov. 8, 1988 , in the names of Robert J. Wojnarowski and Charles W. Eichelberger, entitled "Multichip Integrated Circuit Packaging Configuration and Method" also discloses an interconnection technique relevant to that utilized as part of the invention herein, which application is assigned to the same assignee as the instant application, said application being incorporated herein by reference.